In today's rapidly advancing semiconductor manufacturing industry, there is a push for higher and higher levels of integration and smaller and smaller device features. Various structures and techniques have been developed to enable the increased levels of integration. For example, spacers are typically used alongside (transistor) gate structures formed on semiconductor substrates, to isolate gate contacts from source and drain contacts. Spacers formed of both an oxide liner and a bulk nitride portion are commonly favored in today's semiconductor manufacturing industry. One particularly favored spacer includes an “L-shaped” oxide liner that typically extends along the side of the gate structure and on the semiconductor substrate beneath a nitride portion, with the nitride portion forming the greater portion of the spacer. Various techniques have been developed which enable the production of gate structures of smaller dimensions and associated spacers.
When the other processes used in semiconductor manufacturing operations, however, attack the gate structure and/or the spacers, device integrity and device yield are compromised and device failure may be the result. For example, an RPO is commonly formed over gate structures including the spacers, to protect the underlying structure during subsequent processing operations performed on the other structures of the semiconductor substrate. The RPO may be patterned to expose portions of the underlying structures to be silicided, while protecting other portions from being silicided, for example. The etching processes used to pattern the RPO may attach underlying structures such as oxide portions of spacers. Additionally, the RPO must eventually be removed, typically using a combination of dry and wet processing operations that preferentially attack oxides. When the RPO is etched or removed from over a conventional gate structure using conventional processing operations, underlying oxides may be attached and voids or divots may be produced at the corners of spacer structures in which the oxide liner extends to the outer spacer surface. In particular, when voids occur along the oxide liner formed as the bottom portion of a spacer, and which lies along the semiconductor substrate surface, the voids can result in leakage when subsequent implanting operations, silicidation operations or other similar operations are carried out. Such leakage can cause device failures, or at the least, degrade yield and compromise device integrity.
It would therefore be desirable to produce a gate structure including a spacer, that includes an oxide liner that is immune to damage when an RPO layer is formed over the structure, patterned, and subsequently removed.